1. Field of the Invention
The present invention relates to the formation of a conductor trace-bearing carrier substrate from semiconductor material and the fabrication of a multi-chip module (xe2x80x9cMCMxe2x80x9d) from the substrate. More particularly, the present invention relates to forming the semiconductor carrier substrate as a segment of a micromachined silicon wafer and fabricating the MCM therefrom.
2. State of the Art
Chip On Board (xe2x80x9cCOBxe2x80x9d) techniques are used to attach semiconductor dice to a printed circuit board, including flip chip attachment, wirebonding, and tape automated bonding (xe2x80x9cTABxe2x80x9d). Flip chip attachment consists of attaching a xe2x80x9cflip chipxe2x80x9d to a printed circuit board or other substrate. A flip chip is a semiconductor chip that has a pattern or array of terminations spaced around an active surface of the flip chip for face-down mounting of the flip chip to a substrate. Generally, the flip chip active surface has one of the following electrical connectors: Ball Grid Array (xe2x80x9cBGAxe2x80x9d)xe2x80x94wherein an array of minute solder balls or other conductive material elements is disposed on the electrical connection locations on the active surface of a flip chip that attaches to the substrate, or Slightly Larger than Integrated Circuit Carrier (xe2x80x9cSLICCxe2x80x9d)xe2x80x94which is similar to a BGA, but having a smaller solder ball/conductive material element pitch (spacing) and diameter than a BGA.
Flip chip attachment requires (in the case of solder ball connections) the formation of solder-joinable contact sites or terminals on the metal conductors of a carrier substrate such as a printed circuit board (xe2x80x9cPCBxe2x80x9d), which sites are a mirror-image of the solder ball arrangement on the flip chip. The terminals on the substrate are usually surrounded by non-wettable barriers so that when the solder balls of the bond pads are placed in contact with the chip contact sites to melt and merge (xe2x80x9creflowxe2x80x9d), surface tension holds the semiconductor chip by solder columns, suspending it above the substrate. After cooling, the chip is essentially brazed face-down to the carrier substrate by these very small, closely-spaced solder column interconnections. An insulative underfill encapsulant, such as an epoxy, is then generally disposed between the semiconductor die and the substrate for environmental protection and to enhance the attachment of the die to the substrate.
Higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits are ongoing goals of the computer industry. To meet these challenges, attention has been directed to wafer level packaging. U.S. Pat. No. 4,670,770 issued Jun. 2, 1987 to Tai (xe2x80x9cthe ""770 patentxe2x80x9d) illustrates wafer level integrated circuits formed by placing xe2x80x9cflippedxe2x80x9d semiconductor chips on a wafer substrate. The wafer substrate carries solder metal contacts for attaching to metallic contacts on the semiconductor chips. However, the ""770 patent requires specialized metallic contacts on the semiconductor chips to make contact with the solder metal contacts on the wafer substrate. These specialized contacts increase the cost of manufacturing the assembly because of the additional fabrication steps required.
Silicon wafers have also been used as carrier substrates for temporary electrical connection with an unpackaged semiconductor die for testing, such as disclosed in commonly-owned U.S. Pat. Nos. 5,326,428, 5,478,779, 5,483,741, 5,559,444, and U.S. patent application Ser. No. 08/387,687, each hereby incorporated herein by reference. The patents and application generally disclose raised contact members with sloped walls formed on a silicon wafer by an anisotropic etch process. The raised contact members have one or more projections at their outer ends adapted to penetrate contact locations (bond pads) on the semiconductor die under test and to pierce any residual oxide or other insulating material on the surface of the semiconductor die bond pads to establish an ohmic connection therewith. However, as these projections penetrate the surface of the die bond pads, on the semiconductor die under test to ensure good electrical connection, such penetration may, in some instances, degrade the physical integrity of the bond pad, or might pierce right through the bond pads making physical contact to the devices underneath, damaging and destroying them.
None of the prior art uses of wafers in wafer level semiconductor die packaging and testing as described above teach a cost efficient method of forming a wafer level carrier substrate which can be used for packaging or testing of semiconductor dice, and that does not require any specialized processing steps or which will not damage the bond pads of the semiconductor chip. Furthermore, these prior art techniques address only temporary connection between the bond pads and the substrate. Therefore, it would be advantageous to develop a technique for forming a carrier substrate from a silicon wafer which would achieve these goals while utilizing known semiconductor device fabrication techniques.
The present invention enables semiconductor packaging at a wafer level by forming an MCM from a micromachined carrier substrate, preferably of silicon. The formation of the micromachined substrate begins with providing a substrate of semiconductor material such as monocrystalline silicon (traditional wafer), silicon-on-glass, or silicon-on-sapphire, germanium, or ceramic, which is coated on one surface with a masking material, such as a layer of silicon nitride (Si3N4). The mask material is selectively etched to form strips across the surface of the substrate. The substrate is then etched except under the protective mask strips to form elongated mesas having sidewalls extending to a lower substrate surface. It is, of course, understood that groups of the strips may be placed in mutually transverse orientation to form xe2x80x9cbox canyonsxe2x80x9d of mesas adapted to receive a semiconductor chip with bond pads arrayed about the periphery of its active surface.
After mesa formation, the remaining mask material is removed, preferably using a wet etch. An insulating or dielectric layer is then formed on the substrate, including the elongated mesas and sidewalls. The insulating layer is preferably formed by oxidizing the substrate and may be accomplished by exposing the substrate to an oxidizing atmosphere in a reaction chamber. Other insulating techniques include deposition of silicon dioxide or silicon nitride by chemical vapor deposition (CVD), and injecting TEOS (tetraethyl-orthosilane) into the reaction chamber to grow silicon dioxide (SiO2) at a temperature of about 400xc2x0 C. Silicon dioxide is preferred due to its low dielectric constant, which results in reduced capacitance and increased signal speed on the substrate traces. Other dielectrics such as silicon nitride can also be employed.
A conductive material layer is then formed on the insulating layer. The conductive material layer can be any known low-resistivity material such as a metal, preferably copper. The conductive material layer is then patterned and etched to form or define conductive traces on the dielectric-covered substrate surface. The conductive traces can be patterned to route signals between semiconductor dice carried on the substrate and/or to circuitry external to the substrate. A stack of conductive materials such as copper-coated palladium can also be used.
It is understood that the conductive traces can be formed by a number of alternate conventional techniques other than patterning and etching a metal layer discussed above, such as: depositing a conductive paste on the substrate by silk screening the conductive traces directly thereon; directly extruding a conductive paste to form the conductive traces; or applying a second insulating layer on the first insulating layer, etching a trough in the second insulating layer, filling the trough with a conductive material, and removing the excess conductive material. The conductive traces are preferably formed in the vicinity of chip-mounting sites to include a portion which extends to and over a mesa defining a chip site, down the sidewall and onto a lower, previously-etched portion of the substrate where a chip is to be mounted.
The forming of the conductive traces on a semiconductor substrate devoid of any integrated circuitry enables the conductive traces to be made of copper or any other low resistivity material, because such a substrate can be processed at extremely elevated temperatures (as high as 1000xc2x0 C.) since the substrate does not contain any temperature sensitive integrated circuitry. Substrates containing such integrated circuitry are limited to upper temperatures ranging from about 500 to 700xc2x0 C.
Once the conductive traces are formed on the substrate, they may be brought into input/output communication with external circuitry along a substrate edge with wirebonds, leads, clips, TAB tape attachment, or other connectors known in the art.
Optionally, a passivation layer may be applied over the substrate and conductive traces, which layer is then selectively etched to expose only discrete contact areas on the conductive traces.
When the completed semiconductor carrier substrate comprises an entire wafer, it can be used as a burn-in test substrate. Thus, an integrated circuitry-carrying (IC) wafer with electric contact points corresponding to the conductive traces on the completed semiconductor substrate allows for the testing of the entire circuitry-carrying wafer through burn-in without the need for preliminary dicing of the IC wafer into individual dice for testing. When performing such a burn-in test, it is preferable that the coefficient of thermal expansion (CTE) for the carrier substrate be the same or about the same as that of the IC wafer. Thus, a micromachined silicon carrier substrate is an ideal test bed for a silicon integrated circuit wafer.
A variety of semiconductor dice and/or circuitry-carrying wafer configurations (collectively, xe2x80x9csemiconductor elementsxe2x80x9d) may be attached to the silicon carrier substrate. In general, a standard bond pad array on the semiconductor die, such as a central row or rows, parallel side rows, rectangular periphery arrangement, or combinations thereof, with a conventional bond pad pitch of about 2-3 mils or 75-150 microns, can be used in the present invention. However, if necessary to prevent potential shorting, the bond pad arrangement on the active surface of the die can be rerouted to achieve a sufficiently greater pitch for use with the present invention, although such rerouting is undesirable from a cost standpoint. Furthermore, if the carrier substrate and integrated circuitry-bearing wafer each comprise entire wafers, dicing of these wafers into individual packages for use in a computer system may not be necessary.
Electrical contact between the carrier substrate and semiconductor element is achieved with conductive connectors formed on either the semiconductor element, the carrier substrate, or both (although not preferred as incurring extra cost). The conductive connectors each preferably make contact with both the portion of the conductive trace extending down the mesa sidewall adjacent a chip mounting site and the portion of the conductive trace on the etched portion of the substrate at the site itself. This enhanced, even substantially doubled, contact surface area results in the following advantages:
1. The bond has a lower contact resistance.
2. The bond is more robust than single contact (conventional flat terminal) attachment to the carrier substrate.
3. The bond is stronger, and thus mechanically more reliable.
4. An underfill material may not be required to strengthen the chip-to-substrate attachment.
5. The mesa sidewall acts at least as a rough alignment guide in at least one X-Y direction. When the conductive connectors are solder balls, reflowing the solder achieves an automatic fine alignment due to wetting of the conductive traces carried on the mesa sidewalls.
If parallel, elongated mesas are closely spaced to accommodate the width of a single connector such as a solder ball, the conductive connectors may even make contact with a trace portion extending down a sidewall, a contiguous second portion lying flat on the etched portion of the substrate, and a contiguous third portion extending up a sidewall of an adjacent mesa. This xe2x80x9ctriplexe2x80x9d surface area contact achieves all of the above advantages for the xe2x80x9cdoublexe2x80x9d surface area contact, as well as providing an even stronger bond.
The semiconductor element, such as a large, single semiconductor die or a larger circuitry-bearing substrate such as a wafer or partial wafer, may also straddle the mesa(s) to make electrical contact with various conductive traces placed xe2x80x9coutsidexe2x80x9d of the mesas. Additionally, the conductive connectors on the semiconductor element may be angled to form a matched angular attachment to both the substrate and mesa sidewall portions of the conductive traces. This feature may be employed with non-solder conductive elements such as conductive epoxies or conductor-filled epoxies, as well as with solder conductive connectors wherein a single reflow is employed for attachment of a semiconductor element to substrate traces.
The present invention also includes a stacked configuration of semiconductor elements and carrier substrates. After attachment of semiconductor elements, the resulting semiconductor carrier substrate assemblies can be stacked to form a high density stacked configuration.
An advantage of the present invention is that the carrier substrates of the invention are particularly adapted to the use of xe2x80x9cpartialxe2x80x9d memories. Partials are individual semiconductor memory dice which do not yield the design or expected number of bits, such as when a 64 MB memory die as a DRAM yields only, for example, 37 MB. Rather than scrapping such partials, conductive traces or bit lines can be connected to two or more such xe2x80x9cpartialxe2x80x9d dice to form a larger array of usable memory. This process using the inventive substrate makes use of the lower-yielding, less desirable partials, thereby increasing the overall wafer yield. Furthermore, this bit line process for using partials can also be used for full-capacity memory dice. For example, 120 or more memory dice (or equivalent partial wafer segments) of 16 MB each could result in a multi-gigabit memory array usable in lieu of a hard disk drive in a computer.